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发表于 2005-4-20 19:39:51
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其他cpu切换到smm的方法。
The only processors which support entering SMM directly (ie. without
using the chipset to assert SMI#) are some old AMD 80486 processors,
and many Cyrix processors.
On these AMD 80486s one could set DR7.bit12=1, and then execute F1h,
to enter SMM.
See http://www.sandpile.org/80x86/ia32/drx.shtml for DR7 details.
Many Cyrix parts support the SMINT instruction (0Fh,7Eh for any pre-
6x86MX, or 0Fh,38h for the 6x86MX), if certain conditions (see Cyrix
AP-107 for details) are met.
See http://www.sandpile.org/80x86/opcodes2.shtml for SMINT details.
See http://www.sandpile.org/80x86/ccr.shtml for Cyrix CCRs details.
As for SMBASE there are two methods of changing it. Usually you will
find an entry for it in the state save map. After entering SMM it is
possible to change this SMBASE entry. The P5-core processors require
a 32KB-aligned value, whereas the P6-core processors should take any
value. If an invalid value is used, then the processor will shutdown
on RSM, else it will load the internal SMBASE register with this new
value you specified in the state save map.
See http://www.sandpile.org/80x86/ia32/smm.shtml for SMM details.
The second method is to use RDSHR/WRSHR. These instructions can only
be found on Cyrix 6x86MX processors though.
See http://www.sandpile.org/80x86/opcodes2.shtml for RDMSR/WRMSR.
To summarize this:
1. There is no way to enter SMM via software, except for (a) making
use of chipset (South Bridge) programming, or (b) using a method
which will work only on "niche" processors.
2. The SMBASE register can only be changed via changing an entry in
the state save map, except for using instructions which will not
work on anything but a "niche" processor. |
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